Integrated circuit (IC) logic cells typically consist of a pre-designed layout of transistors or non-specific collection of logic gates which are configured according to a set of rules such as design rules (e.g. minimum wire widths, minimum spacing between structures, etc.), timing rules, and antenna rules, among others. A plurality of such pre-designed or standard IC cells, each having a unique configuration and/or logical function, is referred to as a cell library. To form an IC, such as an application specific IC (ASIC), standard cells are selected from the cell library and arranged in a desired layout. The terminals of the arranged cells are then connected to each other and to external terminals or pins by metal wires to achieve the desired logical function of the IC.
This layout and wiring process is often referred to as the “place and route” step and is typically performed by automated “place and route tools” or “routers”. Although configured in accordance with a set of applicable design rules, router-created wires are not always ideal for manufacturing and yield. For example, routers often employ minimum width wires when thicker wires, which are less sensitive to defect induced interruptions (“opens”) than thinner wires, could be used. Routers also often place wires at minimum separation distances even when larger separation distances, which are less sensitive to defect induced bridges (“shorts”), could be used. Additionally, because routers typically assign wires to routing tracks which are at a regular pitch, unnecessary jogs are often created in wires when connecting wires to pins.
Furthermore, interaction between structures of the standard cell and those added by the router sometimes create complicated shapes, referred to as “ugly shapes”, which are often, but not exclusively, near wire ends where the wire connects to via holes that vertically connect layers of the IC. These ugly shapes can introduce several problems. First, they increase data volume (i.e. file size) and runtimes of subsequent algorithms, such as those employed for optical proximity correction (OPC). They can also confuse such downstream algorithms or cause them to be more complication and error-prone. For example, when optimizing a wire end, an OPC algorithm must detect first the wire end and then make appropriate modifications. Both stops are more complicated if wire ends come in many and unpredictable variants.
Ugly shapes also create multiple variants of a structure within a cell. Because different variants of a structure have different “acceptance regions” (i.e. the manufacturing parameter space within which a structure is successfully fabricated), the “total acceptance region” (i.e. the intersection of all individual acceptance regions) will shrink. The main manufacturing parameters of the lithography processes used to form the ICs are exposure dose, focus, and misalignment. Ugly shapes which reduce or limit the acceptance region of the lithography parameters are referred to as “litho hot spots” and can reduce the reliability of the IC (by increasing the sensitivity to opens and shorts) and reduce manufacturing yield.
In upper metal layers (e.g. above Metal 1), several post-processing techniques (i.e. applied to the “incoming layout” wiring layout after it is provided by a router) have been employed to address the above described shortcomings. One technique, sometimes referred to as “hot spot fixing”, involves performing a lithography simulation to predict the shape of structures (e.g. wires, vias) which will ultimately be formed in a wafer using a given lithography process. Shapes identified as being problematic (i.e. litho hot spots) are attempted to be manually or automatically modified in hopes of eliminating the hot spot. Such a technique works well if the shapes are simple and there is enough space in the neighborhood to enable such modifications. However, if the shapes are complicated and structures are densely packed, fixing one hot spot may create new hot spots in the neighborhood. This process is also time-consuming and costly, does not always identify all hot spots, and depends on the reliability of the lithography model employed, which may vary between manufacturing sites.
Another post-processing technique employs an algorithm which widens wires (e.g. wires which are at a minimum width when more space is available) and increases spacing between neighboring wires (e.g. wires at minimum spacing when more space is available) of the incoming wiring layout provided by a router. Using dimensions which are somewhat larger than the minimum dimensions which can be manufactured by a given lithography process helps to avoid hot spots. However, current versions of one such technique, sometimes referred to as spreading, fattening, and filling (SFF); because it also inserts fill structures, modify only long, straight portions of wires. Line ends and non-trivial or complicated shapes, including jogs and so-called ugly shapes, are not addressed and remain unchanged by SFF. Leaving such shapes unchanged while modifying other portions of a wire can lead to unnecessary jogs being created in a wire and potentially to the inadvertent creation of ugly shapes.
FIG. 1 is an illustrative example of a portion of a router-provided incoming wire layout 30 for an upper metal layer (i.e. above a first metal layer, M1), such as a second metal layer (M2). Jogs 32, 34, and 36 are respectively shown in wires 38, 40, and 42. FIG. 2 illustrates a modified wire layout 30′ resulting from the application of the SFF process to incoming wire layout 30 of FIG. 1 which “spreads” (i.e. increases spacing between wires to greater than design rule minimum) and “fattens” (i.e. increases the width of wires to greater than design rule minimum) the wires of incoming wire layout 30
Comparing modified wire layout 30′ of FIG. 2 to incoming wire layout 30 of FIG. 1, it is apparent that most wires, or at least portions of most wires, have increased widths (i.e. have been “fattened”) and are at increased spacing from one another (i.e. have been “spread”). As part of the SFF process, it is also evident that jogs are inserted as required to maintain at least minimum spacing between wires and/or portions of wires. However, as illustrated by the region within dashed circle 44, because jogs 32, 34, and 36 are not addressed by the SFF process, series of otherwise unnecessary jogs need to be inserted in wires 38, 40, and 42 by the SFF process which can potentially lead to the creation of litho hot spots in modified wire layout 30′.